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		(comment 2 "27 components / 13 nets")
		(comment 3 "Fab: jlc-filled-via")
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		"OUTPUT"
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		(at 17.28 46.88 0)
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		"J1 pin 1 is +24 V, pin 2 is GND."
		(at 17.28 50.88 0)
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		"F1 resettable PTC: Ihold 1.1 A, Vmax 33 V."
		(at 17.28 53.42 0)
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		"D1 Schottky in series blocks reverse polarity."
		(at 17.28 55.96 0)
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	(text
		"D2 TVS (30 V standoff) sits after D1, directly on the VIN node. Its 48.4 V clamp is below U1's 85 V absolute maximum, so U1 stays within its rating under a surge the TVS can absorb."
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		(at 18.55 118 0)
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	(text
		"C1 bulk, C2 ceramic, C3 high-frequency next to the VIN pin (LMR38010 section 9.2.2.6: at least 4.7 uF + 100 to 220 nF)."
		(at 18.55 122 0)
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		"50 V parts for a 24 V rail; DC-bias derating of C2 is not known."
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	(text
		"EN divider from VIN. LMR38010 VEN-H 1.25 V typical (1.1 to 1.4), VEN-L 1.10 V typical: start 18.4 V (16.2 to 20.6 V), stop 16.2 V."
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		"EN stays under 2 V at a 28 V input (EN absolute maximum is VIN + 0.3 V)."
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	(text
		"LMR38010SDDAR: internal compensation, exposed pad (pin 9) on GND, open-drain PG, PFM with spread spectrum."
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		"R_RT 33k from RT/SYNC to GND sets 800 kHz (RT table under datasheet Figure 8-4); the pin must not float."
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		"C4 100 nF boot capacitor between BOOT and SW."
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	(text
		"L1 6.8 uH at 800 kHz gives about 0.5 A ripple at 26.4 V in (datasheet Eq 10 K about 0.5), above the 1.03 uH minimum of Eq 11 (0.25 x 3.3 V / 800 kHz); 3x 22 uF is unverified: Table 9-1 has no 3.3 V row."
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	(text
		"The exposed pad (pin 9) is soldered to the F.Cu GND pour. There are no vias in the pad:"
		(at 18.48 214.71 0)
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	(text
		"the board's fabrication floor is a 0.3 mm drill and the KiCad thermal-via footprint ships 0.2 mm."
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		(at 208.17 44.34 0)
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	(text
		"Vout = 1.0 V x (1 + 100k / 43.2k) = 3.31 V."
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		"Divider taps the output node on the far side of L1, not SW."
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	(text
		"C7 56 pF feed-forward across the upper resistor (datasheet Eq 9 gives about 60 pF)."
		(at 208.17 53.42 0)
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		(at 290.43 128.16 0)
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	(text
		"PG is open drain and pulled up to +3V3 through 100k (datasheet 8.3.5: pull up through a resistor; PG tolerates 20 V)."
		(at 290.43 132.16 0)
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	(text
		"PG goes low during start-up and on a fault, so J2 pin 3 reads valid only after the 4 ms start-up delay."
		(at 290.43 134.7 0)
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	(text
		"D4 green fault LED from +3V3 through R_PGLED to PG: it is lit while PG is low, dark while power is good."
		(at 290.43 137.24 0)
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	(text
		"About 2.5 mA when lit (470 R, Vf about 2.1 V); U1's PG pull-down is about 92 ohm RDSON, so PG stays near 0.4 V."
		(at 290.43 139.78 0)
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		(at 289.3 219.6 0)
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	(text
		"J2 pin 1 is +3.3 V, pin 2 GND, pin 3 power-good (3.3 V logic, 100k pull-up), pin 4 GND."
		(at 289.3 223.6 0)
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	(text
		"D3 green power LED from the 3.3 V rail."
		(at 289.3 226.14 0)
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		(at 319.96 43.07 0)
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	(text
		"Two M2.5 non-plated holes in opposite corners; the board is fixed down through them."
		(at 319.96 47.07 0)
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